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ics8344ayi-01 revision a february 29, 2012 1 ?2012 integrated device technology, inc. low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer ics8344i-01 data sheet le nd q 8 8 8 0 1 pulldown pulldown pullup pulldown pullup pullup pullup clk0 clk_sel clk_en oe nclk0 clk1 nclk1 q[0:7] q[8:15] q[16:23] general description the ics8344i-01 is a low voltage, low skew fanout buffer. the ics8344i-01 has two selectable clock inputs. the clkx, nclkx pairs can accept most standard differential input levels. the ics8344i-01 is designed to translate any differential signal level to lvcmos/lvttl levels. the low impedance lvcmos/lvttl outputs are designed to drive 50 ? series or parallel terminated transmission lines. the effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. redundant clock applications can make use of the dual clock inputs which also facilitate board level testin g. the clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. the outputs are driven low when disabled. the ics8344i-01 is characterized at full 3.3v, full 2.5v and mixed 3.3v input and 2.5v output operating supply modes. guaranteed output and part-to-part skew characteristics make the ics8344i-01 ideal for those clock distribution applications demanding well defined performance and repeatability. features ? twenty-four lvcmos/lvttl outputs, 7 ? typical output impedance ? two selectable differential clkx, nclkx inputs ? clk0, nclk0 and clk1, nclk1 pairs can accept the following input levels: lvds, lvpecl, lvhstl, hcsl ? maximum output frequency: 100mhz ? translates any single ended input signal to lvcmos/lvttl with resistor bias on nclk input ? synchronous clock enable ? additive phase jitter, rms: 0.21ps (typical) ? output skew: 200ps (maximum) ? part-to-part skew: 900ps (maximum) ? bank skew: 180ps (maximum) ? propagation delay: 5ns (maximum) ? output supply modes: core/output 3.3v/3.3v 2.5v/2.5v 3.3v/2.5v ? -40c to 70c ambient operating temperature ? available in lead-free (rohs 6) package 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 q16 q17 v ddo gnd q18 q19 q20 q21 v ddo gnd q22 q23 q7 q6 v ddo gnd q5 q4 q3 q2 v ddo gnd q1 q0 clk_sel gnd v dd nclk1 clk1 gnd v dd nclk0 clk0 clk_en oe nc q14 gnd v ddo q13 q12 q11 q10 gnd v ddo q9 q8 q15 48 47 46 45 44 43 42 41 40 39 38 37 ics8344i-01 48-lead lqfp 7mm x 7mm x 1.4mm package body y package top view pin assignment block diagram
ics8344ayi-01 revision a february 29, 2012 2 ?2012 integrated device technology, inc. ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2, 5, 6, 7, 8, 11, 12 q16, q17, q18, q19, q20, q21, q22, q23 output single-ended clock outputs. 7 ? typical output impedance. lvcmos/lvttl interface levels. 3, 9, 28, 34, 39, 45 v ddo power output supply pins. 4, 10, 14, 18, 27, 33, 40, 46 gnd power power supply ground. 13 clk_sel input pulldown clock select input. when high, sele cts clk1, nclk i nputs, when low, selects clk0, nclk0 inputs. lvcmos / lvttl interface levels. 15, 19 v dd power power supply pins. 16 nclk1 input pullup inverting differential clock input. 17 clk1 input pulldown non-inverting differential clock input. 20 nclk0 input pullup inverting differential clock input. 21 clk0 input pulldown non-inverting differential clock input. 22 clk_en input pullup synchronizing control for enabling and disabling clock outputs. lvcmos / lvttl interface levels. 23 oe input pullup output enable. controls enabling and disabling of outputs q[0:23]. lvcmos / lvttl interface levels. 24 nc unused no connect. 25, 26, 29, 30, 31, 32, 35, 36 q0, q1, q2, q3, q4, q5, q6, q7 output single-ended clock outputs. 7 ? typical output impedance. lvcmos/lvttl interface levels. 37, 38, 41, 42, 43, 44, 47, 48 q8, q9, q10, q11, q12, q13, q14, q15 output single-ended clock outputs. 7 ? typical output impedance. lvcmos/lvttl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4pf c pd power dissipation capacitance (per output) v dd = v ddo = 3.465v 23 pf v dd = v ddo = 2.625v 16 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance v ddo = 3.3v5% or 2.5v5% 7 ?
ics8344ayi-01 revision a february 29, 2012 3 ?2012 integrated device technology, inc. ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer function tables table 3a. output enable function table note 1: the clock enable and disable function is synchron ous to the falling edge of the selected reference clock. table 3a. clock select function table table 3c. clock input function table note 1: please refer to the application information section, wiring the differential input to accept single-ended levels. control input outputs oe clk_en q[0:23] 0 x high-impedance 1 0 disabled in logic low state; note 1 1 1 enabled; note 1 control input clock clk_sel clk0, nclk0 clk1, nclk1 0 selected de-selected 1 de-selected selected inputs outputs input to output mode polarity oe clk0, clk1 nclk0, nclk1 q[0:23] 1 (default) 0 (default) 1 (default) low dif ferential to single-ended non-inverting 1 1 0 high differential to single-ended non-inverting 1 0 biased; note 1 low single-ended to single-ended non-inverting 1 1 biased; note 1 high single-ended to single-ended non-inverting 1 biased; note 1 0 high single-ended to single-ended inverting 1 biased; note 1 1 low single-ended to single-ended inverting
ics8344ayi-01 revision a february 29, 2012 4 ?2012 integrated device technology, inc. ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddo = 3.3v 5%, or v dd = v ddo = 2.5v 5%, or v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = -40c to 70c table 4b. lvcmos/lvttl dc characteristics, t a = -40c to 70c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 53.9 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v 2.375 2.5 2.625 v v ddo output supply voltage 3.135 3.3 3.465 v 2.375 2.5 2.625 v i dd power supply current 95 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd = 3.465v 2 3.8 v v dd = 2.625v 2 2.9 v v il input low voltage v dd = 3.465v -0.3 0.8 v v dd = 2.625v -0.3 0.8 v i ih input high current oe, clk_en v dd = v in = 3.465v or 2.625v 5 a clk_sel v dd = v in = 3.465v or 2.625v 150 a i il input low current oe, clk_en v dd = 3.465v or 2.625v, v in = 0v -150 a clk_sel v dd = 3.465v or 2.625v, v in = 0v -5 a v oh output high voltage v ddo = 3.135v, i oh = -36ma 2.7 v v ddo = 2.375v, i oh = -27ma 1.9 v v ol output low voltage v ddo = 3.135v, i ol = 36ma 0.5 v v ddo = 2.375v, i ol = 27ma 0.5 v
ics8344ayi-01 revision a february 29, 2012 5 ?2012 integrated device technology, inc. ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer table 4c. differential dc characteristics, v dd = v ddo = 3.3v 5%, or v dd = v ddo = 2.5v 5%, or v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = -40c to 70c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . ac electrical characteristics table 5. ac characteristics, v dd = v ddo = 3.3v 5%, or v dd = v ddo = 2.5v 5%, or v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = -40c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters measured at 100mhz and v pp_ typ unless noted otherwise. note 1: measured from the differential input crossing point to v ddo /2. note 2: defined as skew within a bank of outputs at the same voltages and with equal load conditions. note 3: defined as skew across banks of outputs at t he same supply voltages and with equal load conditions. note 4: defined as between outputs at the same supply voltages and with equal load conditions. measured at v ddo /2. note 5: these parameters are guaranteed by characterization. not tested in production. note 6: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditio ns minimum typical maximum units i ih input high current nclk0, nclk1 v dd = v in = 3.465v or 2.625v 5 a clk0, clk1 v dd = v in = 3.465v or 2.625v 150 a i il input low current nclk0, nclk1 v dd = 3.465v or 2.625v, v in = 0v -150 a clk0, clk1 v dd = 3.465v or 2.625v, v in = 0v -5 a v pp peak-to-peak voltage; note 1 0.3 1.3 v v cmr common mode input voltage; note 1, 2 0.9 2.0 v symbol parameter test conditions minimum typical maximum units f out output frequency 100 mhz t pd propagation delay; note 1 f 100mhz 2.5 5 ns t jit buffer additive phase jitter, rms; refer to additive phase jitter section 100mhz, integration range: 12khz ? 20mhz 0.21 ps t sk(b) bank skew; note 2, 6 q[0:7] measured on the rising edge of v ddo /2 155 ps q[8:15] 180 ps q[16:23] 140 ps t sk(o) output skew; note 3, 6 measured on the rising edge of v ddo /2 200 ps t sk(pp) part-to-part skew; note 4, 6 measured on the rising edge of v ddo /2 900 ps t r / t f output rise/fall time; note 5 30% to 70% 200 800 ps t en output enable time; note 5 f = 10mhz 5 ns t dis output disable time; note 5 f = 10mhz 4 ns odc output duty cycle f 100mhz 45 55 %
ics8344ayi-01 revision a february 29, 2012 6 ?2012 integrated device technology, inc. ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamen tal frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device me ets the noise floor of what is shown, but can actually be lowe r. the phase noise is dependent on the input source and measurement equipment. the source generator used is, "agilent e5052a signal source analyzer". ssb phase noise dbc/hz offset from carr ier frequency (hz)
ics8344ayi-01 revision a february 29, 2012 7 ?2012 integrated device technology, inc. ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer parameter measureme nt information 3.3v output load ac test circuit 3.3v core/2.5v output load ac test circuit output skew 2.5v output load ac test circuit differential input level part-to-part skew scope qx gnd v dd, 1.65v5% -1.65v5% v ddo scope qx lvcmos v ddo 2 gnd 2.05v5% -1.25v5% v dd v ddo 1.25v5% t sk(o) v ddo 2 v ddo 2 qx qy scope qx gnd 1.25v5% -1.25v5% v dd, v ddo nclk[0:1] clk[0:1] v dd gnd v cmr cross points v pp t sk(pp) v ddo 2 v ddo 2 part 1 part 2 qx qy
ics8344ayi-01 revision a february 29, 2012 8 ?2012 integrated device technology, inc. ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer parameter measurement in formation, continued propagation delay output duty cycle/pulse width/period output rise/fall time t pd v ddo 2 clk0, clk1 q[0:23] nclk0, nclk1 t period t pw t period odc = v ddo 2 x 100% t pw q[0:23] 30% 70% 70% 30% t r t f q[0:23]
ics8344ayi-01 revision a february 29, 2012 9 ?2012 integrated device technology, inc. ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer application information recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the us e of the differential input, both clkx and nclkx can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clkx to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos outputs can be left floating. there should be no trace attached. wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration re quires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels
ics8344ayi-01 revision a february 29, 2012 10 ?2012 integrated device technology, inc. ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer differential clock input interface the clkx /nclkx accepts lvds , lvpecl, lvhstl, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the clkx/nclkx input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver co mponent to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 2a. clk/nclk input driven by an idt open emitter lvhstl driver figure 2c. clk/nclk input driven by a 3.3v lvpecl driver figure 2e. clk/nclk input driven by a 3.3v hcsl driver figure 2b. clk/nclk input driven by a 3.3v lvpecl driver figure 2d. clk/nclk input driven by a 3.3v lvds driver r1 50 ? r2 50 ? 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt lvhstl driver differential input r3 125 ? r4 125 ? r1 84 ? r2 84 ? 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl differential input hcsl *r3 33 ? *r4 33 ? clk nclk 3.3v 3.3v zo = 50 ? zo = 50 ? differential input r1 50 ? r2 50 ? *optional ? r3 and r4 can be 0 ? clk nclk differential input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 ? r2 50 ? r2 50 ? 3.3v r1 100 ? lvds clk nclk 3.3v receiver zo = 50 ? zo = 50 ?
ics8344ayi-01 revision a february 29, 2012 11 ?2012 integrated device technology, inc. ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer power considerations this section provides information on power dissipati on and junction temperatur e for the ics8344i-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8344i-01 is the sum of th e core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. power (core) max = v dd_max * i dd = 3.465v *95ma = 329.2mw output impedance r out power dissipation due to loading 50 ? to v dd /2 output current i out = v dd_max / [2 * (50 ? + r out )] = 3.465v / [2 * (50 ? + 7 ? )] = 30.4ma power dissipation on the r out per lvcmos output power (r out ) = r out * (i out ) 2 = 7 ? * (30.4ma) 2 = 6.47mw per output total power (r out ) = 6.47mw * 24 = 155mw dynamic power dissipation at 100mhz power (100mhz) = c pd * frequency * (v dd ) 2 = 16pf * 100mhz * (3.465v) 2 = 19.2mw per output total power (100mhz) = 19.2mw * 24 = 461mw total power dissipation total power = power (core) max + power (r out ) + power (100mhz) = 329.2mw + 155mw + 461mw = 945.2mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 81.2c/w per table 6 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.945w *53.9c/w = 120.9c. th is is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 48 lead lqfp, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 53.9c/w 47.7c/w 45.0c/w
ics8344ayi-01 revision a february 29, 2012 12 ?2012 integrated device technology, inc. ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer reliability information table 7. ja vs. air flow table for a 48 lead lqfp transistor count the transistor count for ics8344i-01 is: 1503 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 53.9c/w 47.7c/w 45.0c/w
ics8344ayi-01 revision a february 29, 2012 13 ?2012 integrated device technology, inc. ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer package outline and package dimensions package outline - y suffix for 48 lead lqfp table 7. package dimensions for 48 lead lqfp reference document: jedec publication 95, ms-026 jedec variation: abc - hd all dimensions in millimeters symbol minimum nominal maximum n 48 a 1.60 a1 0.05 0.10 0.15 a2 1.35 1.4 1.45 b 0.17 0.22 0.27 c 0.09 0.15 0.20 d & e 9.00 basic d1 & e1 7.00 basic d2 & e2 5.50 ref. e 0.50 basic l 0.45 0.60 0.75 0 7 ccc 0.08
ics8344ayi-01 revision a february 29, 2012 14 ?2012 integrated device technology, inc. ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer ordering information table 8. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 8344ayi-01lf ics8344ai01l ?lead-free? 48 lead lqfp tray -40 c to 70c 8344AYI-01ILFT ics8344ai01l ?lead-free? 48 lead lqfp 1000 tape & reel -40 c to 70c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, wh ich would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ics8344i-01 data sheet low skew, 1-to-24 di fferential-to-lvcmos/lvttl fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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